The cell array of a NOR-type flash memory device includes a plurality of memory cells in the row and column directions, and bit-line contacts for accessing each memory cell. U.S. Pat. No. 6,197,639 titled “Method for Manufacturing NOR-Type Flash Memory Device” describes a method of forming a bit-line contact for a NOR-type flash memory device using a self-aligned contact (“SAC”).
FIGS. 1-3 are cross-sectional views illustrating a conventional method of forming a NOR-type flash memory cell.
Referring to FIG. 1, a field isolation layer 12 is formed at a semiconductor substrate 10 to define an active region 14. A tunnel oxide layer 16 is formed on the active region 14 and a plurality of gate patterns 26 are formed on the tunnel oxide layer 16. Each of the gate patterns 26 comprises a floating gate 18, an inter-gate dielectric layer 20, a control gate electrode 22 and a capping layer 24 that are sequentially stacked. Impurities are implanted into the active region 14 between the gate patterns 26, thereby forming a source region 32s and a drain region 32d. A spacer pattern 28 is formed on the sidewalls of the gate pattern 26, and a planarized interlayer dielectric layer 30 is formed over the surface of the semiconductor substrate 10. The spacer pattern 28 and the interlayer dielectric layer 30 are formed of materials that have etch selectivity with respect to each other.
As shown in FIG. 2, the interlayer dielectric layer 30 is patterned to form contact holes exposing the source region 32s and the drain region 32d. During the patterning, the spacer pattern 28 acts as an etch stopping layer. Thus, the contact hole 34 is self-aligned by the spacer pattern 28. Then, as shown in FIG. 3, the contact holes 34 are filled with a conductive material to form a source contact pattern 36s connected to the source region 32s and a drain contact pattern 36d connected to the drain region 32d. 
FIG. 4 is depicts a cell array of a conventional NOR-type flash memory device. As shown in FIG. 4, the cell array includes a plurality of data blocks 00, 01, . . . 0n, . . . , n0, n1, . . . nn. Each of the data blocks includes a plurality of memory cells that are arranged in rows and columns. A plurality of parallel word lines WL are provided that run in the row direction, and a plurality of parallel bit lines BL are provided that run in the column direction. Each memory cell is connected to one of the word lines and one of the bit lines. In a NOR-type flash memory device, a specific word line and a specific bit line may be selected to access a specific memory cell. Thus, reading operations can be independently performed on a specific memory cell. However, in order to reduce the operation time, erase operations are performed by data block. In particular, the erase operation is performed simultaneously on all of the memory cells of a particular data block after pre-programming the data block. However, because the memory cells typically are not structurally uniform, the memory cells may not erase uniformly, and a single erase pulse may fail to successfully erase every memory cell in the data block. Consequently, to erase the memory cells in a data block, the erase operation (and verification thereof) is typically performed a predetermined number of times. As the number of times the erasing and verification operations are performed becomes large, so does the time required to erase the data block.